diff --git a/tests/integration_tests.rs b/tests/integration_tests.rs
index d6523366..038e8683 100644
--- a/tests/integration_tests.rs
+++ b/tests/integration_tests.rs
@@ -2612,7 +2612,7 @@ fn lessopen_validity() {
 // Syntax highlighting should be the same regardless of
 // --map-syntax' case or file extension's case
 #[test]
-fn highlighting_independant_from_map_syntax_case() {
+fn highlighting_independent_from_map_syntax_case() {
     let expected = bat()
         .arg("-f")
         .arg("--map-syntax=*.config:JSON")
diff --git a/tests/syntax-tests/highlighted/Verilog/div_pipelined.v b/tests/syntax-tests/highlighted/Verilog/div_pipelined.v
index 81a7c96a..d42015db 100644
--- a/tests/syntax-tests/highlighted/Verilog/div_pipelined.v
+++ b/tests/syntax-tests/highlighted/Verilog/div_pipelined.v
@@ -13,7 +13,7 @@
 // limitations under the License.
 
 // Implements a fixed-point parameterized pipelined division
-// operation. Outputs are expected to be on range [-1,1), techincally
+// operation. Outputs are expected to be on range [-1,1), technically
 // [-1,2^(BITS-1)-1/2^(BITS-1)]. There is no convergent rounding.
 //
 // [TODO] Implement optional convergent rounding and some form of
diff --git a/tests/syntax-tests/source/Solidity/ERC721.sol b/tests/syntax-tests/source/Solidity/ERC721.sol
index b617f3d2..5cdb2aa9 100644
--- a/tests/syntax-tests/source/Solidity/ERC721.sol
+++ b/tests/syntax-tests/source/Solidity/ERC721.sol
@@ -98,7 +98,7 @@ contract ERC721 is Context, ERC165, IERC721, IERC721Metadata {
     }
 
     /**
-     * @dev Base URI for computing {tokenURI}. Empty by default, can be overriden
+     * @dev Base URI for computing {tokenURI}. Empty by default, can be overridden
      * in child contracts.
      */
     function _baseURI() internal view virtual returns (string memory) {
diff --git a/tests/syntax-tests/source/Verilog/div_pipelined.v b/tests/syntax-tests/source/Verilog/div_pipelined.v
index b8460fb4..6f9f8e06 100644
--- a/tests/syntax-tests/source/Verilog/div_pipelined.v
+++ b/tests/syntax-tests/source/Verilog/div_pipelined.v
@@ -13,7 +13,7 @@
 // limitations under the License.
 
 // Implements a fixed-point parameterized pipelined division
-// operation. Outputs are expected to be on range [-1,1), techincally
+// operation. Outputs are expected to be on range [-1,1), technically
 // [-1,2^(BITS-1)-1/2^(BITS-1)]. There is no convergent rounding.
 //
 // [TODO] Implement optional convergent rounding and some form of