mirror of https://framagit.org/kyodev/kyopages.git
cpu_flags
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# attention: remplacer index par les encadrés "", ex:
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# DSCPL ⟷ "ds_cpl" CPL Qual. Debug Store par DS_CPL ⟷ _CPL Qual. Debug Store
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# https://github.com/torvalds/linux/blob/master/arch/x86/include/asm/cpufeatures.h
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# 11/2017
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## Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0
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FPU ⟷ Onboard FPU
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VME ⟷ Virtual Mode Extensions
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DE ⟷ Debugging Extensions
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PSE ⟷ Page Size Extensions
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TSC ⟷ Time Stamp Counter
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MSR ⟷ Model-Specific Registers
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PAE ⟷ Physical Address Extensions
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MCE ⟷ Machine Check Exception
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CX8 ⟷ CMPXCHG8 instruction
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APIC ⟷ Onboard APIC
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SEP ⟷ SYSENTER/SYSEXIT
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MTRR ⟷ Memory Type Range Registers
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PGE ⟷ Page Global Enable
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MCA ⟷ Machine Check Architecture
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CMOV ⟷ CMOV instructions (plus FCMOVcc, FCOMI with FPU)
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PAT ⟷ Page Attribute Table
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PSE36 ⟷ 36-bit PSEs
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PN ⟷ Processor serial number
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CLFLUSH ⟷ CLFLUSH instruction
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DTS ⟷ Debug Store
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ACPI ⟷ ACPI via MSR
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MMX ⟷ Multimedia Extensions
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FXSR ⟷ FXSAVE/FXRSTOR, CR4.OSFXSR
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SSE ⟷ sse
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SSE2 ⟷ sse2
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SS ⟷ CPU self snoop
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HT ⟷ Hyper-Threading
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TM ⟷ Automatic clock control
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IA64 ⟷ IA-64 processor
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PBE ⟷ Pending Break Enable
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## AMD-defined CPU features, CPUID level 0x80000001, word 1 Don't duplicate feature flags which are redundant with Intel!
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SYSCALL ⟷ SYSCALL/SYSRET
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MP ⟷ MP Capable.
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NX ⟷ Execute Disable
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MMXEXTAMD ⟷ MMX extensions
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FXSR_OPT ⟷ FXSAVE/FXRSTOR optimizations
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PDPE1GB ⟷ GB pages
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RDTSCP ⟷ RDTSCP
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LM ⟷ Long Mode (x86-64)
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3DNOWEXT ⟷ AMD 3DNow! extensions
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3DNOW ⟷ 3DNow!
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## Transmeta-defined CPU features, CPUID level 0x80860001, word 2
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RECOVERY ⟷ CPU in recovery mode
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LONGRUN ⟷ Longrun power control
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LRTI ⟷ LongRun table interface
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## Other features, Linux-defined mapping, word 3 This range is used for feature bits which conflict or are synthesized
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CXMMX ⟷ Cyrix MMX extensions
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K6_MTRR ⟷ AMD K6 nonstandard MTRRs
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CYRIX_ARR ⟷ Cyrix ARRs (= MTRRs)
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CENTAUR_MCR ⟷ Centaur MCRs (= MTRRs)
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## cpu types for specific tunings:
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K8 ⟷ Opteron, Athlon64
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K7 ⟷ Athlon
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P3 ⟷ P3
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P4 ⟷ P4
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CONSTANT_TSC ⟷ TSC ticks at a constant rate
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UP ⟷ smp kernel running on up
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ART ⟷ Platform has always running timer (ART)
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ARCH_PERFMON ⟷ Intel Architectural PerfMon
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PEBS ⟷ Precise-Event Based Sampling
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BTS Branch ⟷ Trace Store
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SYSCALL32 ⟷ syscall in ia32 userspace
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SYSENTER32 ⟷ sysenter in ia32 userspace
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REP_GOOD ⟷ rep microcode works well
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MFENCE_RDTSC ⟷ Mfence synchronizes RDTSC
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LFENCE_RDTSC ⟷ Lfence synchronizes RDTSC
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ACC_POWERAMD ⟷ Accumulated Power Mechanism
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NOPL ⟷ instructions
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ALWAYS ⟷ Always-present feature
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XTOPOLOGY ⟷ cpu topology enum extensions
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TSC_RELIABLE ⟷ TSC is known to be reliable
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NONSTOP_TSC ⟷ TSC does not stop in C states
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CPUID ⟷ CPU has CPUID instruction itself
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EXTD ⟷ APICID has extended APICID (8 bits)
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AMD_DCM ⟷ multi-node processor
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APERFMPERF ⟷ APERFMPERF
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NONSTOP_TSC_S3 ⟷ TSC doesn't stop in S3 state
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TSC_KNOWN_FREQ ⟷ TSC has known frequency
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## Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4
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PNI ⟷ SSE-3
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PCLMULQDQ ⟷ PCLMULQDQ instruction
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DTES64 ⟷ 64-bit Debug Store
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MONITOR ⟷ Monitor/Mwait support
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DS_CPL ⟷ CPL Qual. Debug Store
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VMX ⟷ Hardware virtualization
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SMX ⟷ Safer mode
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EST ⟷ Enhanced SpeedStep
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TM2 ⟷ Thermal Monitor 2
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SSSE3 ⟷ Supplemental SSE-3
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CID ⟷ Context ID
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SDBG ⟷ Silicon Debug
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FMA ⟷ Fused multiply-add
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CX16 ⟷ CMPXCHG16B
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XTPR ⟷ Send Task Priority Messages
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PDCM ⟷ Performance Capabilities
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PCID ⟷ Process Context Identifiers
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DCA ⟷ Direct Cache Access
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SSE4_1 ⟷ SSE-4.1
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SSE4_2 ⟷ SSE-4.2
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X2APIC ⟷ x2APIC
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MOVBE ⟷ MOVBE instruction
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POPCNT ⟷ POPCNT instruction
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TSC_DEADLINE_TIMER ⟷ Tsc deadline timer
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AES ⟷ AES instructions
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XSAVE ⟷ XSAVE/XRSTOR/XSETBV/XGETBV
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OSXSAVE ⟷ XSAVE enabled in the OS
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AVX ⟷ Advanced Vector Extensions
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F16C ⟷ 16-bit fp conversions
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RDRAND ⟷ The RDRAND instruction
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HYPERVISOR ⟷ Running on a hypervisor
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## VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5
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RNG ⟷ RNG present (xstore)
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RNG_EN ⟷ RNG enabled
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ACE ⟷ on-CPU crypto (xcrypt)
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ACE_EN ⟷ on-CPU crypto enabled
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ACE2 ⟷ Advanced Cryptography Engine v2
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ACE2_EN ⟷ ACE v2 enabled
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PHE ⟷ PadLock Hash Engine
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PHE ⟷ ENPHE enabled
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PMM ⟷ PadLock Montgomery Multiplier
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PMM_EN ⟷ PMM enabled
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## More extended AMD flags: CPUID level 0x80000001, ecx, word 6
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LAHF_LM ⟷ LAHF/SAHF in long mode
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CMP_LEGACY ⟷ If yes HyperThreading not valid
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SVM ⟷ Secure virtual machine
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EXTAPIC ⟷ Extended APIC space
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CR8_LEGACY ⟷ CR8 in 32-bit mode
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ABM ⟷ Advanced bit manipulation
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SSE4A ⟷ SSE-4A
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MISALIGNSSE ⟷ Misaligned SSE mode
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3DNOWPREFETCH ⟷ 3DNow prefetch instructions
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OSVWOS ⟷ Visible Workaround
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IBS ⟷ Instruction Based Sampling
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XOP ⟷ extended AVX instructions
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SKINIT ⟷ SKINIT/STGI instructions
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WDT ⟷ Watchdog timer
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LWP ⟷ Light Weight Profiling
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FMA44 ⟷ operands MAC instructions
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TCE ⟷ translation cache extension
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NODEID ⟷ MSRNodeId MSR
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TBM ⟷ trailing bit manipulations
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TOPOEXT ⟷ topology extensions CPUID leafs
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PERFCTR_CORE ⟷ core performance counter extensions
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PERFCTR_NB ⟷ NB performance counter extensions
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BPEXT ⟷ data breakpoint extension
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PTSC ⟷ performance time-stamp counter
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PERFCTR_LLC ⟷ Last Level Cache performance counter extensions
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MWAITX ⟷ MWAIT extension (MONITORX/MWAITX)
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## Auxiliary flags: Linux defined - For features scattered in various CPUID levels like 0x6, 0xA etc, word 7.
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RING3MWAIT ⟷ Ring 3 MONITOR/MWAIT
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CPUID_FAULT ⟷ Intel CPUID faulting
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CPB ⟷ AMD Core Performance Boost
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EPB ⟷ IA32_ENERGY_PERF_BIAS support
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CAT_L3 ⟷ Cache Allocation Technology L3
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CAT_L2 ⟷ Cache Allocation Technology L2
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CDP_L3 ⟷ Code and Data Prioritization L3
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HW_PSTATE ⟷ AMD HW-PState
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PROC_FEEDBACK ⟷ AMD ProcFeedbackInterface
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SME ⟷ AMD Secure Memory Encryption
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INTEL_PPIN ⟷ Intel Processor Inventory Number
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INTEL_PT ⟷ Intel Processor Trace
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AVX512_4VNNIW ⟷ AVX-512 Neural Network Instructions
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AVX512_4FMAPS ⟷ AVX-512 Multiply Accumulation Single precision
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MBA ⟷ Memory Bandwidth Allocation
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## Virtualization flags: Linux defined, word 8
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TPR_SHADOW ⟷ Intel TPR Shadow
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VNMI ⟷ Intel Virtual NMI
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FLEXPRIORITY ⟷ Intel FlexPriority
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EPT ⟷ Intel Extended Page Table
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VPID ⟷ Intel Virtual Processor ID
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VMMCALL ⟷ Prefer vmmcall to vmcall
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XENPV ⟷ Xen paravirtual guest
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## Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9
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FSGSBASE ⟷ {RD/WR}{FS/GS}BASE instructions*/
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TSC_ADJUST ⟷ TSC adjustment MSR 0x3b
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BMI1 ⟷ 1st group bit manipulation extensions
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HLE ⟷ Hardware Lock Elision
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AVX2 ⟷ AVX2 instructions
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SMEP ⟷ Supervisor Mode Execution Protection
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BMI2 ⟷ 2nd group bit manipulation extensions
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ERMS ⟷ Enhanced REP MOVSB/STOSB
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INVPCID ⟷ Invalidate Processor Context ID
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RTM ⟷ Restricted Transactional Memory
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CQM ⟷ Cache QoS Monitoring
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MPX ⟷ Memory Protection Extension
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RDT_A ⟷ Resource Director Technology Allocation
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AVX512F ⟷ AVX-512 Foundation
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AVX512DQ ⟷ AVX-512 DQ (Double/Quad granular) Instructions
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RDSEED ⟷ The RDSEED instruction
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ADX ⟷ The ADCX and ADOX instructions
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SMAP ⟷ Supervisor Mode Access Prevention
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AVX512IFMA ⟷ AVX-512 Integer Fused Multiply-Add instructions
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CLFLUSHOPT ⟷ CLFLUSHOPT instruction
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CLWB ⟷ CLWB instruction
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AVX512PF ⟷ AVX-512 Prefetch
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AVX512ER ⟷ AVX-512 Exponential and Reciprocal
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AVX512CD ⟷ AVX-512 Conflict Detection
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SHA_NI ⟷ SHA1/SHA256 Instruction Extensions
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AVX512BW ⟷ AVX-512 BW (Byte/Word granular) Instructions
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AVX512VL ⟷ AVX-512 VL (128/256 Vector Length) Extensions
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#Extended state features, CPUID level 0x0000000d:1 (eax), word 10
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XSAVEOPT ⟷ XSAVEOPT
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XSAVEC ⟷ XSAVEC
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XGETBV1 ⟷ XGETBV with ECX = 1
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XSAVES ⟷ XSAVES/XRSTORS
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## Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (edx), word 11
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CQM_LLC ⟷ LLC QoS if 1
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## Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12
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CQM_OCCUP_LLC ⟷ LLC occupancy monitoring if 1
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CQM_MBM_TOTAL ⟷ LLC Total MBM monitoring
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CQM_MBM_LOCAL ⟷ LLC Local MBM monitoring
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## AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13
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CLZERO ⟷ CLZERO instruction
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IRPERF ⟷ Instructions Retired Count
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## Thermal and Power Management Leaf, CPUID level 0x00000006 (eax), word 14
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DTHERM ⟷ Digital Thermal Sensor
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IDA ⟷ Intel Dynamic Acceleration
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ARAT ⟷ Always Running APIC Timer
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PLN ⟷ Intel Power Limit Notification
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PTS ⟷ Intel Package Thermal Status
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HWP ⟷ Intel Hardware P-states
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HWP_NOTIFY ⟷ HWP Notification
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HWP_ACT_WINDOW ⟷ HWP Activity Window
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HWP_EPP ⟷ HWP Energy Perf. Preference
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HWP_PKG_REQ ⟷ HWP Package Level Request
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## AMD SVM Feature Identification, CPUID level 0x8000000a (edx), word 15
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NPT ⟷ Nested Page Table support
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LBRVLBR ⟷ Virtualization support
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SVM_LOCK ⟷ SVM locking MSR
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NRIP_SAVE ⟷ SVM next_rip save
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TSC_SCALE ⟷ TSC scaling support
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VMCB_CLEAN ⟷ VMCB clean bits support
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FLUSHBYASID ⟷ flush-by-ASID support
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DECODEASSISTS ⟷ Decode Assists support
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PAUSEFILTER ⟷ filtered pause intercept
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PFTHRESHOLD ⟷ pause filter threshold
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AVIC ⟷ Virtual Interrupt Controller
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V_VMSAVE_VMLOAD ⟷ Virtual VMSAVE VMLOAD
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VGIF ⟷ Virtual GIF
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## Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 16
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AVX512VBMI ⟷ AVX512 Vector Bit Manipulation instructions*/
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PKU ⟷ Protection Keys for Userspace
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OSPKEOS ⟷ Protection Keys Enable
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AVX512_VPOPCNTDQ ⟷ POPCNT for vectors of DW/QW
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LA57 ⟷ 5-level page tables
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RDPID ⟷ RDPIDinstruction
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## AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17
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OVERFLOW_RECOV ⟷ MCA overflow recovery support
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SUCCOR ⟷ Uncorrectable error containment and recovery
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SMCA ⟷ Scalable MCA
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@ -0,0 +1,64 @@
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09/2016
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https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-2a-manual.pdf
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table 3.10 registre ECX
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table 3.10 registre ECX
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ACPI Thermal Monitor and Software Controlled Clock Facilities.
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AESNI support the AESNI instruction extensions.
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APIC APIC On-Chip.
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AVX support the AVX instruction extensions.
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CLFSH CLFLUSH Instruction.
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CMOV Conditional Move Instructions.
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CMPXCHG16B CMPXCHG16B feature.
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CNXT-ID L1 Context ID.
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CX8 CMPXCHG8B Instruction.
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DCA supports the ability to prefetch data from a memory mapped device.
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DE Debugging Extensions.
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DS-CPL CPL Debug Store.
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DS Debug Store.
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DTES64 64-bit DS Area. The processor supports DS area using 64-bit layout.
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EIST Enhanced Intel SpeedStep® technology.
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F16C support 16-bit floating-point conversion instructions.
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FMA support FMA extensions using YMM state.
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FPU Floating Point Unit On-Chip. The processor contains an x87 FPU.
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FXSR FXSAVE and FXRSTOR Instructions.
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HTT Max APIC IDs reserved field is Valid.
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MCA Machine Check Architecture.
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MCE Machine Check Exception.
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MMX Intel MMX Technology.
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MONITOR MONITOR/MWAIT.
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MOVBE support MOVBE instruction.
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MSR Model Specific Registers RDMSR and WRMSR Instructions.
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MTRR Memory Type Range Registers.
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OSXSAVE the OS has set CR4.OSXSAVE[bit 18] to enable XSETBV/XGETBV instructions to access XCR0 and to support processor extended state management using XSAVE/XRSTOR.
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PAE Physical Address Extension.
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PAT Page Attribute Table.
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PBE Pending Break Enable.
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PCID Process-context identifiers.
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PCLMULQDQ PCLMULQDQ instruction.
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PDCM Perfmon and Debug Capability
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PGE Page Global Bit.
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POPCNT support the POPCNT instruction.
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PSE-36 36-Bit Page Size Extension.
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PSE Page Size Extension.
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PSN Processor Serial Number.
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RDRAND support RDRAND instruction.
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SDBG support IA32_DEBUG_INTERFACE MSR for silicon debug.
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SEP SYSENTER and SYSEXIT Instructions.
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SMX Safer Mode Extensions.
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SSE2 SSE2.
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SSE3 Streaming SIMD Extensions 3 (SSE3).
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SSE4.1 support SSE4.1.
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SSE4.2 support SSE4.2.
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SSE SSE.
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SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3).
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SS Self Snoop.
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TM2 Thermal Monitor 2.
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TM Thermal Monitor.
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TSC-Deadline the processor’s local APIC timer supports one-shot operation using a TSC deadline value.
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TSC Time Stamp Counter.
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VME Virtual 8086 Mode Enhancements.
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VMX Virtual Machine Extensions
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x2APIC x2APIC feature.
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XSAVE support the XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV instructions, and XCR0.
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xTPR Update Control xTPR Update Control. The processor supports changing IA32_MISC_ENABLE[bit 23].
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@ -0,0 +1,106 @@
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intel
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family 04) "Intel 80486, 1000 à 600nm";; # arch_x86, 1989-2007
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family 05)
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01 | 02 | 03 | 07 "Intel P5 (Pentium), 800, 600, 500, 350nm";; # arch_x86, 1993, 5V, 3.3V
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04 | 08 "Intel P5 (Pentium MMX), 280, 250nm";; # arch_x86, 1996
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09 "Intel Quark";; # arch_x86
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family 0B)
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01 Knights Corner (Xeon Phi) # arch_x86?
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family 0F
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00 | 01 | 02 NetBurst P68 (P4), 180, 130nm # arch_x86? 2000
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03 | 04 Prescott NetBurst P68, 90nm # arch_x86?
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06 Presler NetBurst P68 # arch_x86?
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family 06
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01 "Intel P6 (i686) (Pentium Pro)";; # arch_x86, 1995
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03 | 04 | 05 P6 Prescott (Pentium II) 90nm # arch_x86
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06 P6 Prescott (Pentium II) 65nm # arch_x86
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07 | 08 | 0A | 0B P6 (Pentium III) # arch_x86
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09 | 0D | 15 P6 Dothan (Pentium M) 90nm # arch_x86 2003
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0E Core, 65nm # arch_x86, 2006
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0F | 16 Merom (Core2) 65nm
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17 | 1D Penryn (Core2) 45nm
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1A | 1E | 1F | 2E Nehalem 45nm
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25 | 2C | 2F Westmere 32nm
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2A | 2D Sandy Bridge 32nm
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3A | 3E Ivy Bridge 22nm
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3C | 3F | 45 | 46 Haswell 22nm
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3D | 47 | 4F | 56 Broadwell 14nm
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4E) "Intel Skylake 14nm (Y/U-Processor Lines)";; # 6th Generation intel doc 332689-011 06/2017 https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/desktop-6th-gen-core-family-spec-update.pdf xeon doc 333133-017U 09/2017 https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-e3-1200v5-spec-update.pdf
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5E) "Intel Skylake 14nm (H/S-Processor Lines)";; # 6th Generation intel doc 332689-011 06/2017 https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/desktop-6th-gen-core-family-spec-update.pdf xeon doc 333133-017U 09/2017 https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-e3-1200v5-spec-update.pdf
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55) "Intel Skylake 14nm";; # existe? vu sur cpuinfo
|
||||
8E) "Intel Kaby Lake 14nm (Y/U/U-Quad Core-Processor Lines)";; # 7/8th Generation intel doc 334663-009 08/2017 https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/7th-gen-core-family-spec-update.pdf
|
||||
9E) "Intel Kaby Lake 14nm (S/H/X-Processor Lines)";; # 7/8th Generation intel doc 334663-009 08/2017 https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/7th-gen-core-family-spec-update.pdf
|
||||
xx coffee lake 14nm # 10/2017
|
||||
xx skymont (cannonlake) 10nm # 2018
|
||||
xx icelake 10nm # 2018 ou 2019
|
||||
xx tigerlake 10nm # 2019 gen12
|
||||
xx sapphire rapids 7nm # 2020 gen12
|
||||
|
||||
# Atom
|
||||
1C | 26 Bonnell 45nm
|
||||
27 |35 |36 Saltwell 32nm
|
||||
37 | 4A | 4D | 5A Silvermont 22nm
|
||||
4C | 5D | 5F Airmont 14nm
|
||||
|
||||
?? 5F "Intel Atom (Goldmont), 14nm") ??
|
||||
xx Goldmont 14nm
|
||||
xx Goldmont+ 14nm
|
||||
|
||||
# Knights-series cores
|
||||
57 knights_landing
|
||||
85) "Intel Knights Mill (Xeon Phi), 14nm";; # no spéc mais Volume 3C Table 35-1 326019-060
|
||||
|
||||
https://software.intel.com/sites/default/files/managed/22/0d/335592-sdm-vol-4.pdf
|
||||
335592-064 October 2017 Software Developer’s Manual vol 4
|
||||
https://software.intel.com/en-us/articles/intel-sdm
|
||||
|
||||
amd
|
||||
family 05, model 0A ??? Geode # compatible x86 proc, Cyrix->NS->AMD référencé sur cpuinfo
|
||||
|
||||
family 04) # arch_x86
|
||||
03 | 07 | 08 | 09 | 0A) "AMD Am486";; # années 90
|
||||
0E | 0F) "AMD Am5x86, 350nm";; # 1995-1999
|
||||
*) fg_uarch="AMD ?86 $defaut_model";;
|
||||
|
||||
family 05) # arch_x86
|
||||
00 | 01 | 02 | 03) "AMD K5 SSA/5 ou 5k86, 350nm";; # 1996
|
||||
06 | 07) "AMD K6 350, 250nm";; # 1997-1998
|
||||
08) "AMD K6-2, 250nm";; # 1998-1999
|
||||
09 | 0D) "AMD K6-3 Sharptooth, 250, 180nm";; # 1999-2000
|
||||
*) fg_uarch="AMD K5/K6 $defaut_model";;
|
||||
|
||||
family 06) "AMD K7 Athlon, 250, 180, 130nm, (Classic/T-Bird/Palomino/T-Bred/Barton and Thorton";; # arch_x86 1999-2005
|
||||
|
||||
family 0F) # 2003-?
|
||||
0? | 1?) "AMD K8 Hammer (SledgeHammer), 130-65nm";;
|
||||
2?) "AMD K8 Hammer (SledgeHammer) (rev.E), 130-65nm";;
|
||||
4? | 5? | 6? | 7? | C?) "AMD K8 Hammer (SledgeHammer) (rev.F+), 130-65nm";;
|
||||
*) fg_uarch="AMD K8 Hammer (SledgeHammer) $defaut_model";;
|
||||
|
||||
family 10) "AMD Barcelona K10, 65, 45, 32nm";; # 2007-2012 Agena, Toliman, Thuban, Deneb, Heka, Callisto, Regor, Propus APU: Llano
|
||||
family 11) "AMD Turion X2 Ultra/Puma mobile, dérivée K8/K10, 65, 45nm";; # mixture of K8/K10 designs with lower power consumption
|
||||
family 12) "AMD Fusion, dérivée K10, 32nm";; # Llano
|
||||
|
||||
family 15)
|
||||
00 | 01) "AMD Bulldozer 1ère génération, 32nm";; # 2011- success to K10,
|
||||
02 | 1?) "AMD Piledriver (Enhanced Bulldozer) (Bulldozer 2e génération), 32nm";; # 2012- APU: Trinity, Richland
|
||||
3?) "AMD Steamroller (Bulldozer 3e génération), 28nm";; # 2014- APU: Kaveri
|
||||
6? | 7?) "AMD Excavator (Bulldozer 4e génération), 28nm";; # 2015- gén. finale APU: Carrizo, Bristol Ridge, Stoney Ridge
|
||||
*) "AMD Bulldozer, $defaut_model";;
|
||||
|
||||
family 17)
|
||||
*) "AMD Zen, 14nm";; # 2017- APU: Raven Ridge
|
||||
|
||||
xxx Zen2 successeur Zen
|
||||
|
||||
# basse consommation
|
||||
family 14) "AMD Bobcat, 40nm";; # 2011- APU: Desna, Ontario, Zacate
|
||||
family 16)
|
||||
0?) "AMD Jaguar 28nm";; # 2013- APU: Kabini, Temash
|
||||
3?) "AMD Puma ou Puma+ (family 16h 2e génération), 28nm";; # 2014- APU: Beema, Mullins, Puma+ APU: Carrizo-L
|
||||
*) fg_uarch="AMD family 16h (Jaguar/Puma) $defaut_model";;
|
||||
|
|
@ -0,0 +1,332 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef _ASM_X86_CPUFEATURES_H
|
||||
#define _ASM_X86_CPUFEATURES_H
|
||||
|
||||
#ifndef _ASM_X86_REQUIRED_FEATURES_H
|
||||
#include <asm/required-features.h>
|
||||
#endif
|
||||
|
||||
#ifndef _ASM_X86_DISABLED_FEATURES_H
|
||||
#include <asm/disabled-features.h>
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Defines x86 CPU feature bits
|
||||
*/
|
||||
#define NCAPINTS 18 /* N 32-bit words worth of info */
|
||||
#define NBUGINTS 1 /* N 32-bit bug flags */
|
||||
|
||||
/*
|
||||
* Note: If the comment begins with a quoted string, that string is used
|
||||
* in /proc/cpuinfo instead of the macro name. If the string is "",
|
||||
* this feature bit is not displayed in /proc/cpuinfo at all.
|
||||
*/
|
||||
|
||||
/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
|
||||
#define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */
|
||||
#define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */
|
||||
#define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */
|
||||
#define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */
|
||||
#define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */
|
||||
#define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */
|
||||
#define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */
|
||||
#define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */
|
||||
#define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */
|
||||
#define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */
|
||||
#define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */
|
||||
#define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */
|
||||
#define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */
|
||||
#define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */
|
||||
#define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions */
|
||||
/* (plus FCMOVcc, FCOMI with FPU) */
|
||||
#define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */
|
||||
#define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */
|
||||
#define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */
|
||||
#define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */
|
||||
#define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */
|
||||
#define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */
|
||||
#define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */
|
||||
#define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */
|
||||
#define X86_FEATURE_XMM ( 0*32+25) /* "sse" */
|
||||
#define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */
|
||||
#define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */
|
||||
#define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */
|
||||
#define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */
|
||||
#define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */
|
||||
#define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */
|
||||
|
||||
/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
|
||||
/* Don't duplicate feature flags which are redundant with Intel! */
|
||||
#define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */
|
||||
#define X86_FEATURE_MP ( 1*32+19) /* MP Capable. */
|
||||
#define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */
|
||||
#define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */
|
||||
#define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */
|
||||
#define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */
|
||||
#define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */
|
||||
#define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64) */
|
||||
#define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow! extensions */
|
||||
#define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow! */
|
||||
|
||||
/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
|
||||
#define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */
|
||||
#define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */
|
||||
#define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */
|
||||
|
||||
/* Other features, Linux-defined mapping, word 3 */
|
||||
/* This range is used for feature bits which conflict or are synthesized */
|
||||
#define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */
|
||||
#define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */
|
||||
#define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */
|
||||
#define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */
|
||||
/* cpu types for specific tunings: */
|
||||
#define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */
|
||||
#define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */
|
||||
#define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */
|
||||
#define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */
|
||||
#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */
|
||||
#define X86_FEATURE_UP ( 3*32+ 9) /* smp kernel running on up */
|
||||
#define X86_FEATURE_ART ( 3*32+10) /* Platform has always running timer (ART) */
|
||||
#define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */
|
||||
#define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */
|
||||
#define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */
|
||||
#define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in ia32 userspace */
|
||||
#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in ia32 userspace */
|
||||
#define X86_FEATURE_REP_GOOD ( 3*32+16) /* rep microcode works well */
|
||||
#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */
|
||||
#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */
|
||||
#define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */
|
||||
#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */
|
||||
#define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */
|
||||
#define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */
|
||||
#define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */
|
||||
#define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */
|
||||
#define X86_FEATURE_CPUID ( 3*32+25) /* CPU has CPUID instruction itself */
|
||||
#define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */
|
||||
#define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */
|
||||
#define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */
|
||||
#define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */
|
||||
#define X86_FEATURE_TSC_KNOWN_FREQ ( 3*32+31) /* TSC has known frequency */
|
||||
|
||||
/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
|
||||
#define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */
|
||||
#define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */
|
||||
#define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */
|
||||
#define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" Monitor/Mwait support */
|
||||
#define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */
|
||||
#define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */
|
||||
#define X86_FEATURE_SMX ( 4*32+ 6) /* Safer mode */
|
||||
#define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */
|
||||
#define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */
|
||||
#define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */
|
||||
#define X86_FEATURE_CID ( 4*32+10) /* Context ID */
|
||||
#define X86_FEATURE_SDBG ( 4*32+11) /* Silicon Debug */
|
||||
#define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */
|
||||
#define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B */
|
||||
#define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */
|
||||
#define X86_FEATURE_PDCM ( 4*32+15) /* Performance Capabilities */
|
||||
#define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */
|
||||
#define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */
|
||||
#define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */
|
||||
#define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */
|
||||
#define X86_FEATURE_X2APIC ( 4*32+21) /* x2APIC */
|
||||
#define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */
|
||||
#define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */
|
||||
#define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* Tsc deadline timer */
|
||||
#define X86_FEATURE_AES ( 4*32+25) /* AES instructions */
|
||||
#define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
|
||||
#define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE enabled in the OS */
|
||||
#define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */
|
||||
#define X86_FEATURE_F16C ( 4*32+29) /* 16-bit fp conversions */
|
||||
#define X86_FEATURE_RDRAND ( 4*32+30) /* The RDRAND instruction */
|
||||
#define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */
|
||||
|
||||
/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
|
||||
#define X86_FEATURE_XSTORE ( 5*32+ 2) /* "rng" RNG present (xstore) */
|
||||
#define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */
|
||||
#define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
|
||||
#define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */
|
||||
#define X86_FEATURE_ACE2 ( 5*32+ 8) /* Advanced Cryptography Engine v2 */
|
||||
#define X86_FEATURE_ACE2_EN ( 5*32+ 9) /* ACE v2 enabled */
|
||||
#define X86_FEATURE_PHE ( 5*32+10) /* PadLock Hash Engine */
|
||||
#define X86_FEATURE_PHE_EN ( 5*32+11) /* PHE enabled */
|
||||
#define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */
|
||||
#define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */
|
||||
|
||||
/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
|
||||
#define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */
|
||||
#define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */
|
||||
#define X86_FEATURE_SVM ( 6*32+ 2) /* Secure virtual machine */
|
||||
#define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */
|
||||
#define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */
|
||||
#define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */
|
||||
#define X86_FEATURE_SSE4A ( 6*32+ 6) /* SSE-4A */
|
||||
#define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* Misaligned SSE mode */
|
||||
#define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* 3DNow prefetch instructions */
|
||||
#define X86_FEATURE_OSVW ( 6*32+ 9) /* OS Visible Workaround */
|
||||
#define X86_FEATURE_IBS ( 6*32+10) /* Instruction Based Sampling */
|
||||
#define X86_FEATURE_XOP ( 6*32+11) /* extended AVX instructions */
|
||||
#define X86_FEATURE_SKINIT ( 6*32+12) /* SKINIT/STGI instructions */
|
||||
#define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */
|
||||
#define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */
|
||||
#define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */
|
||||
#define X86_FEATURE_TCE ( 6*32+17) /* translation cache extension */
|
||||
#define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */
|
||||
#define X86_FEATURE_TBM ( 6*32+21) /* trailing bit manipulations */
|
||||
#define X86_FEATURE_TOPOEXT ( 6*32+22) /* topology extensions CPUID leafs */
|
||||
#define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */
|
||||
#define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */
|
||||
#define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */
|
||||
#define X86_FEATURE_PTSC ( 6*32+27) /* performance time-stamp counter */
|
||||
#define X86_FEATURE_PERFCTR_LLC ( 6*32+28) /* Last Level Cache performance counter extensions */
|
||||
#define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */
|
||||
|
||||
/*
|
||||
* Auxiliary flags: Linux defined - For features scattered in various
|
||||
* CPUID levels like 0x6, 0xA etc, word 7.
|
||||
*
|
||||
* Reuse free bits when adding new feature flags!
|
||||
*/
|
||||
#define X86_FEATURE_RING3MWAIT ( 7*32+ 0) /* Ring 3 MONITOR/MWAIT */
|
||||
#define X86_FEATURE_CPUID_FAULT ( 7*32+ 1) /* Intel CPUID faulting */
|
||||
#define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */
|
||||
#define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */
|
||||
#define X86_FEATURE_CAT_L3 ( 7*32+ 4) /* Cache Allocation Technology L3 */
|
||||
#define X86_FEATURE_CAT_L2 ( 7*32+ 5) /* Cache Allocation Technology L2 */
|
||||
#define X86_FEATURE_CDP_L3 ( 7*32+ 6) /* Code and Data Prioritization L3 */
|
||||
|
||||
#define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */
|
||||
#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
|
||||
#define X86_FEATURE_SME ( 7*32+10) /* AMD Secure Memory Encryption */
|
||||
|
||||
#define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */
|
||||
#define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */
|
||||
#define X86_FEATURE_AVX512_4VNNIW (7*32+16) /* AVX-512 Neural Network Instructions */
|
||||
#define X86_FEATURE_AVX512_4FMAPS (7*32+17) /* AVX-512 Multiply Accumulation Single precision */
|
||||
|
||||
#define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */
|
||||
|
||||
/* Virtualization flags: Linux defined, word 8 */
|
||||
#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
|
||||
#define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */
|
||||
#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */
|
||||
#define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */
|
||||
#define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */
|
||||
|
||||
#define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer vmmcall to vmcall */
|
||||
#define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */
|
||||
|
||||
|
||||
/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */
|
||||
#define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/
|
||||
#define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3b */
|
||||
#define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */
|
||||
#define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */
|
||||
#define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */
|
||||
#define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */
|
||||
#define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */
|
||||
#define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB */
|
||||
#define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */
|
||||
#define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */
|
||||
#define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */
|
||||
#define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */
|
||||
#define X86_FEATURE_RDT_A ( 9*32+15) /* Resource Director Technology Allocation */
|
||||
#define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */
|
||||
#define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */
|
||||
#define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */
|
||||
#define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */
|
||||
#define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */
|
||||
#define X86_FEATURE_AVX512IFMA ( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */
|
||||
#define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */
|
||||
#define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */
|
||||
#define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */
|
||||
#define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */
|
||||
#define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */
|
||||
#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */
|
||||
#define X86_FEATURE_AVX512BW ( 9*32+30) /* AVX-512 BW (Byte/Word granular) Instructions */
|
||||
#define X86_FEATURE_AVX512VL ( 9*32+31) /* AVX-512 VL (128/256 Vector Length) Extensions */
|
||||
|
||||
/* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */
|
||||
#define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */
|
||||
#define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC */
|
||||
#define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 */
|
||||
#define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS */
|
||||
|
||||
/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (edx), word 11 */
|
||||
#define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */
|
||||
|
||||
/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */
|
||||
#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */
|
||||
#define X86_FEATURE_CQM_MBM_TOTAL (12*32+ 1) /* LLC Total MBM monitoring */
|
||||
#define X86_FEATURE_CQM_MBM_LOCAL (12*32+ 2) /* LLC Local MBM monitoring */
|
||||
|
||||
/* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */
|
||||
#define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */
|
||||
#define X86_FEATURE_IRPERF (13*32+1) /* Instructions Retired Count */
|
||||
|
||||
/* Thermal and Power Management Leaf, CPUID level 0x00000006 (eax), word 14 */
|
||||
#define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */
|
||||
#define X86_FEATURE_IDA (14*32+ 1) /* Intel Dynamic Acceleration */
|
||||
#define X86_FEATURE_ARAT (14*32+ 2) /* Always Running APIC Timer */
|
||||
#define X86_FEATURE_PLN (14*32+ 4) /* Intel Power Limit Notification */
|
||||
#define X86_FEATURE_PTS (14*32+ 6) /* Intel Package Thermal Status */
|
||||
#define X86_FEATURE_HWP (14*32+ 7) /* Intel Hardware P-states */
|
||||
#define X86_FEATURE_HWP_NOTIFY (14*32+ 8) /* HWP Notification */
|
||||
#define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */
|
||||
#define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */
|
||||
#define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */
|
||||
|
||||
/* AMD SVM Feature Identification, CPUID level 0x8000000a (edx), word 15 */
|
||||
#define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */
|
||||
#define X86_FEATURE_LBRV (15*32+ 1) /* LBR Virtualization support */
|
||||
#define X86_FEATURE_SVML (15*32+ 2) /* "svm_lock" SVM locking MSR */
|
||||
#define X86_FEATURE_NRIPS (15*32+ 3) /* "nrip_save" SVM next_rip save */
|
||||
#define X86_FEATURE_TSCRATEMSR (15*32+ 4) /* "tsc_scale" TSC scaling support */
|
||||
#define X86_FEATURE_VMCBCLEAN (15*32+ 5) /* "vmcb_clean" VMCB clean bits support */
|
||||
#define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* flush-by-ASID support */
|
||||
#define X86_FEATURE_DECODEASSISTS (15*32+ 7) /* Decode Assists support */
|
||||
#define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */
|
||||
#define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */
|
||||
#define X86_FEATURE_AVIC (15*32+13) /* Virtual Interrupt Controller */
|
||||
#define X86_FEATURE_V_VMSAVE_VMLOAD (15*32+15) /* Virtual VMSAVE VMLOAD */
|
||||
#define X86_FEATURE_VGIF (15*32+16) /* Virtual GIF */
|
||||
|
||||
/* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 16 */
|
||||
#define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/
|
||||
#define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */
|
||||
#define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */
|
||||
#define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */
|
||||
#define X86_FEATURE_LA57 (16*32+16) /* 5-level page tables */
|
||||
#define X86_FEATURE_RDPID (16*32+22) /* RDPID instruction */
|
||||
|
||||
/* AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17 */
|
||||
#define X86_FEATURE_OVERFLOW_RECOV (17*32+0) /* MCA overflow recovery support */
|
||||
#define X86_FEATURE_SUCCOR (17*32+1) /* Uncorrectable error containment and recovery */
|
||||
#define X86_FEATURE_SMCA (17*32+3) /* Scalable MCA */
|
||||
|
||||
/*
|
||||
* BUG word(s)
|
||||
*/
|
||||
#define X86_BUG(x) (NCAPINTS*32 + (x))
|
||||
|
||||
#define X86_BUG_F00F X86_BUG(0) /* Intel F00F */
|
||||
#define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */
|
||||
#define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */
|
||||
#define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */
|
||||
#define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */
|
||||
#define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */
|
||||
#define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */
|
||||
#define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */
|
||||
#define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* SYSRET doesn't fix up SS attrs */
|
||||
#ifdef CONFIG_X86_32
|
||||
/*
|
||||
* 64-bit kernels don't use X86_BUG_ESPFIX. Make the define conditional
|
||||
* to avoid confusion.
|
||||
*/
|
||||
#define X86_BUG_ESPFIX X86_BUG(9) /* "" IRET to 16-bit SS corrupts ESP/RSP high bits */
|
||||
#endif
|
||||
#define X86_BUG_NULL_SEG X86_BUG(10) /* Nulling a selector preserves the base */
|
||||
#define X86_BUG_SWAPGS_FENCE X86_BUG(11) /* SWAPGS without input dep on GS */
|
||||
#define X86_BUG_MONITOR X86_BUG(12) /* IPI required to wake up remote CPU */
|
||||
#define X86_BUG_AMD_E400 X86_BUG(13) /* CPU is among the affected by Erratum 400 */
|
||||
#endif /* _ASM_X86_CPUFEATURES_H */
|
||||
Loading…
Reference in New Issue