mirror of https://framagit.org/kyodev/kyopages.git
maj
This commit is contained in:
parent
1e714e2553
commit
d55318c277
|
@ -51,7 +51,7 @@ VME ⟷ Virtual Mode Extensions
|
|||
3DNOWEXT ⟷ AMD 3DNow! extensions
|
||||
FXSR_OPT ⟷ FXSAVE/FXRSTOR optimizations
|
||||
LM ⟷ Long Mode (x86-64)
|
||||
MMXEXTAMD ⟷ MMX extensions
|
||||
MMXEXT ⟷ AMD MMX extensions
|
||||
MP ⟷ MP Capable.
|
||||
NX ⟷ Execute Disable
|
||||
PDPE1GB ⟷ GB pages
|
||||
|
@ -89,10 +89,10 @@ AMD_DCM ⟷ multi-node processor
|
|||
APERFMPERF ⟷ APERFMPERF
|
||||
ARCH_PERFMON ⟷ Intel Architectural PerfMon
|
||||
ART ⟷ Platform has always running timer (ART)
|
||||
BTS Branch ⟷ Trace Store
|
||||
BTS ⟷ Branch Trace Store
|
||||
CONSTANT_TSC ⟷ TSC ticks at a constant rate
|
||||
CPUID ⟷ CPU has CPUID instruction itself
|
||||
EXTD ⟷ APICID has extended APICID (8 bits)
|
||||
EXTD_APICID ⟷ has extended APICID (8 bits)
|
||||
K7 ⟷ Athlon
|
||||
K8 ⟷ Opteron, Athlon64
|
||||
LFENCE_RDTSC ⟷ Lfence synchronizes RDTSC
|
||||
|
@ -161,8 +161,8 @@ ACE2 ⟷ Advanced Cryptography Engine v2
|
|||
ACE2_EN ⟷ ACE v2 enabled
|
||||
ACE_EN ⟷ on-CPU crypto enabled
|
||||
ACE ⟷ on-CPU crypto (xcrypt)
|
||||
PHE ⟷ ENPHE enabled
|
||||
PHE ⟷ PadLock Hash Engine
|
||||
PHE_EN ⟷ PHE enabled
|
||||
PMM_EN ⟷ PMM enabled
|
||||
PMM ⟷ PadLock Montgomery Multiplier
|
||||
RNG_EN ⟷ RNG enabled
|
||||
|
@ -187,7 +187,7 @@ LAHF_LM ⟷ LAHF/SAHF in long mode
|
|||
LWP ⟷ Light Weight Profiling
|
||||
MISALIGNSSE ⟷ Misaligned SSE mode
|
||||
MWAITX ⟷ MWAIT extension (MONITORX/MWAITX)
|
||||
NODEID ⟷ MSRNodeId MSR
|
||||
NODEID_MSR ⟷ NodeId MSR
|
||||
OSVWOS ⟷ Visible Workaround
|
||||
PERFCTR_CORE ⟷ core performance counter extensions
|
||||
PERFCTR_LLC ⟷ Last Level Cache performance counter extensions
|
||||
|
@ -345,7 +345,7 @@ PTS ⟷ Intel Package Thermal Status
|
|||
AVIC ⟷ Virtual Interrupt Controller
|
||||
DECODEASSISTS ⟷ Decode Assists support
|
||||
FLUSHBYASID ⟷ flush-by-ASID support
|
||||
LBRVLBR ⟷ Virtualization support
|
||||
LBRV ⟷ LBR Virtualization support
|
||||
NPT ⟷ Nested Page Table support
|
||||
NRIP_SAVE ⟷ SVM next_rip save
|
||||
PAUSEFILTER ⟷ filtered pause intercept
|
||||
|
@ -421,7 +421,7 @@ AVX ⟷ Advanced Vector Extensions
|
|||
BMI1 ⟷ 1st group bit manipulation extensions
|
||||
BMI2 ⟷ 2nd group bit manipulation extensions
|
||||
BPEXT ⟷ data breakpoint extension
|
||||
BTS Branch ⟷ Trace Store
|
||||
BTS ⟷ Branch Trace Store
|
||||
CAT_L2 ⟷ Cache Allocation Technology L2
|
||||
CAT_L3 ⟷ Cache Allocation Technology L3
|
||||
CDP_L3 ⟷ Code and Data Prioritization L3
|
||||
|
@ -459,7 +459,7 @@ EPT ⟷ Intel Extended Page Table
|
|||
ERMS ⟷ Enhanced REP MOVSB/STOSB
|
||||
EST ⟷ Enhanced SpeedStep
|
||||
EXTAPIC ⟷ Extended APIC space
|
||||
EXTD ⟷ APICID has extended APICID (8 bits)
|
||||
EXTD_APICID ⟷ has extended APICID (8 bits)
|
||||
F16C ⟷ 16-bit fp conversions
|
||||
FLEXPRIORITY ⟷ Intel FlexPriority
|
||||
FLUSHBYASID ⟷ flush-by-ASID support
|
||||
|
@ -489,7 +489,7 @@ K7 ⟷ Athlon
|
|||
K8 ⟷ Opteron, Athlon64
|
||||
LA57 ⟷ 5-level page tables
|
||||
LAHF_LM ⟷ LAHF/SAHF in long mode
|
||||
LBRVLBR ⟷ Virtualization support
|
||||
LBRV ⟷ LBR Virtualization support
|
||||
LFENCE_RDTSC ⟷ Lfence synchronizes RDTSC
|
||||
LM ⟷ Long Mode (x86-64)
|
||||
LONGRUN ⟷ Longrun power control
|
||||
|
@ -500,7 +500,7 @@ MCA ⟷ Machine Check Architecture
|
|||
MCE ⟷ Machine Check Exception
|
||||
MFENCE_RDTSC ⟷ Mfence synchronizes RDTSC
|
||||
MISALIGNSSE ⟷ Misaligned SSE mode
|
||||
MMXEXTAMD ⟷ MMX extensions
|
||||
MMXEXT ⟷ AMD MMX extensions
|
||||
MMX ⟷ Multimedia Extensions
|
||||
MONITOR ⟷ Monitor/Mwait support
|
||||
MOVBE ⟷ MOVBE instruction
|
||||
|
@ -509,7 +509,7 @@ MPX ⟷ Memory Protection Extension
|
|||
MSR ⟷ Model-Specific Registers
|
||||
MTRR ⟷ Memory Type Range Registers
|
||||
MWAITX ⟷ MWAIT extension (MONITORX/MWAITX)
|
||||
NODEID ⟷ MSRNodeId MSR
|
||||
NODEID_MSR ⟷ NodeId MSR
|
||||
NONSTOP_TSC_S3 ⟷ TSC doesn't stop in S3 state
|
||||
NONSTOP_TSC ⟷ TSC does not stop in C states
|
||||
NOPL ⟷ instructions
|
||||
|
@ -536,8 +536,8 @@ PERFCTR_LLC ⟷ Last Level Cache performance counter extensions
|
|||
PERFCTR_NB ⟷ NB performance counter extensions
|
||||
PFTHRESHOLD ⟷ pause filter threshold
|
||||
PGE ⟷ Page Global Enable
|
||||
PHE ⟷ ENPHE enabled
|
||||
PHE ⟷ PadLock Hash Engine
|
||||
PHE_EN ⟷ PHE enabled
|
||||
PKU ⟷ Protection Keys for Userspace
|
||||
PLN ⟷ Intel Power Limit Notification
|
||||
PMM_EN ⟷ PMM enabled
|
||||
|
|
|
@ -39,7 +39,7 @@ PBE ⟷ Pending Break Enable
|
|||
SYSCALL ⟷ SYSCALL/SYSRET
|
||||
MP ⟷ MP Capable.
|
||||
NX ⟷ Execute Disable
|
||||
MMXEXTAMD ⟷ MMX extensions
|
||||
MMXEXT ⟷ AMD MMX extensions
|
||||
FXSR_OPT ⟷ FXSAVE/FXRSTOR optimizations
|
||||
PDPE1GB ⟷ GB pages
|
||||
RDTSCP ⟷ RDTSCP
|
||||
|
@ -68,7 +68,7 @@ UP ⟷ smp kernel running on up
|
|||
ART ⟷ Platform has always running timer (ART)
|
||||
ARCH_PERFMON ⟷ Intel Architectural PerfMon
|
||||
PEBS ⟷ Precise-Event Based Sampling
|
||||
BTS Branch ⟷ Trace Store
|
||||
BTS ⟷ Branch Trace Store
|
||||
SYSCALL32 ⟷ syscall in ia32 userspace
|
||||
SYSENTER32 ⟷ sysenter in ia32 userspace
|
||||
REP_GOOD ⟷ rep microcode works well
|
||||
|
@ -81,7 +81,7 @@ XTOPOLOGY ⟷ cpu topology enum extensions
|
|||
TSC_RELIABLE ⟷ TSC is known to be reliable
|
||||
NONSTOP_TSC ⟷ TSC does not stop in C states
|
||||
CPUID ⟷ CPU has CPUID instruction itself
|
||||
EXTD ⟷ APICID has extended APICID (8 bits)
|
||||
EXTD_APICID ⟷ has extended APICID (8 bits)
|
||||
AMD_DCM ⟷ multi-node processor
|
||||
APERFMPERF ⟷ APERFMPERF
|
||||
NONSTOP_TSC_S3 ⟷ TSC doesn't stop in S3 state
|
||||
|
@ -128,7 +128,7 @@ ACE_EN ⟷ on-CPU crypto enabled
|
|||
ACE2 ⟷ Advanced Cryptography Engine v2
|
||||
ACE2_EN ⟷ ACE v2 enabled
|
||||
PHE ⟷ PadLock Hash Engine
|
||||
PHE ⟷ ENPHE enabled
|
||||
PHE_EN ⟷ PHE enabled
|
||||
PMM ⟷ PadLock Montgomery Multiplier
|
||||
PMM_EN ⟷ PMM enabled
|
||||
|
||||
|
@ -150,7 +150,7 @@ WDT ⟷ Watchdog timer
|
|||
LWP ⟷ Light Weight Profiling
|
||||
FMA44 ⟷ operands MAC instructions
|
||||
TCE ⟷ translation cache extension
|
||||
NODEID ⟷ MSRNodeId MSR
|
||||
NODEID_MSR ⟷ NodeId MSR
|
||||
TBM ⟷ trailing bit manipulations
|
||||
TOPOEXT ⟷ topology extensions CPUID leafs
|
||||
PERFCTR_CORE ⟷ core performance counter extensions
|
||||
|
@ -252,7 +252,7 @@ HWP_PKG_REQ ⟷ HWP Package Level Request
|
|||
|
||||
## AMD SVM Feature Identification, CPUID level 0x8000000a (edx), word 15
|
||||
NPT ⟷ Nested Page Table support
|
||||
LBRVLBR ⟷ Virtualization support
|
||||
LBRV ⟷ LBR Virtualization support
|
||||
SVM_LOCK ⟷ SVM locking MSR
|
||||
NRIP_SAVE ⟷ SVM next_rip save
|
||||
TSC_SCALE ⟷ TSC scaling support
|
||||
|
|
Loading…
Reference in New Issue