mirror of https://github.com/sharkdp/bat.git
104 lines
2.1 KiB
Systemverilog
104 lines
2.1 KiB
Systemverilog
`timescale 1ns/1ps
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// Design Code
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module ADDER(
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input clk,
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input [7:0] a,
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input [7:0] b,
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input bIsPos,
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output reg [8:0] result
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);
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always @ (posedge clk) begin
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if (bIsPos) begin
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result <= a + b;
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end else begin
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result <= a - b;
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end
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end
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endmodule: ADDER
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interface adder_if(
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input bit clk,
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input [7:0] a,
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input [7:0] b,
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input bIsPos,
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input [8:0] result
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);
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clocking cb @(posedge clk);
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output a;
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output b;
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output bIsPos;
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input result;
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endclocking : cb
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endinterface: adder_if
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bind ADDER adder_if my_adder_if(
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.clk(clk),
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.a(a),
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.b(b),
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.bIsPos(bIsPos),
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.result(result)
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);
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// Testbench Code
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import uvm_pkg::*;
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`include "uvm_macros.svh"
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class testbench_env extends uvm_env;
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virtual adder_if m_if;
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function new(string name, uvm_component parent = null);
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super.new(name, parent);
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endfunction
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function void connect_phase(uvm_phase phase);
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assert(uvm_resource_db#(virtual adder_if)::read_by_name(get_full_name(), "adder_if", m_if));
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endfunction: connect_phase
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task run_phase(uvm_phase phase);
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phase.raise_objection(this);
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`uvm_info(get_name(), "Starting test!", UVM_HIGH);
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begin
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int a = 8'h4, b = 8'h5;
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@(m_if.cb);
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m_if.cb.a <= a;
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m_if.cb.b <= b;
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m_if.cb.bIsPos <= 1'b1;
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repeat(2) @(m_if.cb);
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`uvm_info(get_name(), $sformatf("%0d + %0d = %0d", a, b, m_if.cb.result), UVM_LOW);
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end
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`uvm_info(get_name(), "Ending test!", UVM_HIGH);
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phase.drop_objection(this);
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endtask: run_phase
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endclass
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module top;
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bit clk;
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env environment;
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ADDER dut(.clk (clk));
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initial begin
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environment = new("testbench_env");
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uvm_resource_db#(virtual adder_if)::set("env", "adder_if", dut.my_adder_if);
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clk = 0;
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run_test();
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end
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// Clock generation
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initial begin
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forever begin
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#(1) clk = ~clk;
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end
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end
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endmodule
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